{"id":328,"date":"2017-05-02T20:50:03","date_gmt":"2017-05-03T01:50:03","guid":{"rendered":"https:\/\/knm.org.uk\/blog\/?p=328"},"modified":"2019-05-29T07:59:36","modified_gmt":"2019-05-29T12:59:36","slug":"v86p-expansion","status":"publish","type":"post","link":"https:\/\/knm.org.uk\/blog\/2017\/05\/v86p-expansion\/","title":{"rendered":"V86P Expansion"},"content":{"rendered":"

Retrochallenge RC2017\/04 might be over, but I'm going to try and keep moving on this project. I'd already started on the pinout for the internal connectors used by the hard disk controller, and finishing that off seemed like a fairly straightforward task. Having done that, the Expansion Bus header on the back of the system was just a matter of following the same process.<\/p>\n

I started off with the hard disk controller, a multimeter, and the datasheet for the OMTI 5090 IBM PC Bus Interface<\/a> controller. The datasheet has the pinout for the IC, along with a table identifying which pins were for the system bus, and which were for the system interface. For each of the system interface pins, checked for continuity to each of the pins on the header connecting to the motherboard. This got most of the header identified, with just a few unlabelled pins. To get those, I basically did the same thing on the motherboard, except in this case identifying the signals was more difficult. On the motherboard, many of the signals need to be buffered (or in the case of address lines, latched). For that, Victor just used 74-series logic - 74HCT244 and 74HCT373 specifically, which is well documented. I traced the signals from the connector to the appropriate buffer output, looked up the input on the datasheet, then traced the input back to the main Chips & Tech 82C100<\/a>. From there I could identify the signal.<\/p>\n

<\/p>\n

\"\"<\/a><\/p>\n

There are three headers of interest - two which connect to the motherboard, and another labelled TP1, presumably test points. After ringing out the connectors, the latter may actually be a jumper-block used during testing.<\/p>\n

After getting the pinouts for the connectors to the HDD controller, I repeated the same process for the expansion bus connector - the results of which were pleasantly surprising. It turns out to be essentially the same pinout as a regular 8-bit ISA connector, but with a couple of differences. Firstly, the pins that would typically provide power rails are replaced with ground pins; pins A1 and B1 are not present, with \/IO CH CHK is relocated to pin 13; and pin 7 is replaced with a 4.7k pull-up resistor to Vcc. <\/p>\n

With all that said, here are the pinouts:<\/p>\n

CN1 - to motherboard<\/b><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
A_19<\/td>\n1<\/td>\n2<\/td>\nA_18<\/td>\n<\/tr>\n
Gnd<\/td>\n3<\/td>\n4<\/td>\nGnd<\/td>\n<\/tr>\n
Vcc<\/td>\n5<\/td>\n6<\/td>\nVcc<\/td>\n<\/tr>\n
AEN<\/td>\n7<\/td>\n8<\/td>\nIRQ_5<\/td>\n<\/tr>\n
A_17<\/td>\n9<\/td>\n10<\/td>\nA_16<\/td>\n<\/tr>\n
A_15<\/td>\n11<\/td>\n12<\/td>\nA_14<\/td>\n<\/tr>\n
A_13<\/td>\n13<\/td>\n14<\/td>\nA_12<\/td>\n<\/tr>\n
A_11<\/td>\n15<\/td>\n16<\/td>\nA_10<\/td>\n<\/tr>\n
A_9<\/td>\n17<\/td>\n18<\/td>\nA_8<\/td>\n<\/tr>\n
A_7<\/td>\n19<\/td>\n20<\/td>\nA_6<\/td>\n<\/tr>\n
DRQ_3<\/td>\n21<\/td>\n22<\/td>\nRSTIN<\/td>\n<\/tr>\n
\/DACK_3<\/td>\n23<\/td>\n24<\/td>\nA_5<\/td>\n<\/tr>\n
\/IORD<\/td>\n25<\/td>\n26<\/td>\nA_4<\/td>\n<\/tr>\n
\/IOWR<\/td>\n27<\/td>\n28<\/td>\nA_3<\/td>\n<\/tr>\n
A_2<\/td>\n29<\/td>\n30<\/td>\nA_0<\/td>\n<\/tr>\n
A_1<\/td>\n31<\/td>\n32<\/td>\nGnd<\/td>\n<\/tr>\n
 <\/td>\n33<\/td>\n34<\/td>\n <\/td>\n<\/tr>\n
Vcc<\/td>\n35<\/td>\n36<\/td>\nGnd<\/td>\n<\/tr>\n
Gnd<\/td>\n37<\/td>\n38<\/td>\nVcc<\/td>\n<\/tr>\n
\/MEMR<\/td>\n39<\/td>\n40<\/td>\nGnd<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

 <\/p>\n

CN3 - to motherboard<\/b><\/p>\n\n\n\n\n\n\n
D_0<\/td>\n1<\/td>\n2<\/td>\nD_1<\/td>\n<\/tr>\n
D_2<\/td>\n3<\/td>\n4<\/td>\nD_3<\/td>\n<\/tr>\n
D_4<\/td>\n5<\/td>\n6<\/td>\nD_5<\/td>\n<\/tr>\n
D_6<\/td>\n7<\/td>\n8<\/td>\nD_7<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

 <\/p>\n

TP1<\/b><\/p>\n\n\n\n\n\n\n\n\n\n\n
Gnd<\/td>\n1<\/td>\n9<\/td>\nDT_0<\/td>\n<\/tr>\n
Gnd<\/td>\n2<\/td>\n10<\/td>\nDT_1<\/td>\n<\/tr>\n
Gnd<\/td>\n3<\/td>\n11<\/td>\nDT_2<\/td>\n<\/tr>\n
Gnd<\/td>\n4<\/td>\n12<\/td>\nDT_3<\/td>\n<\/tr>\n
Gnd<\/td>\n5<\/td>\n13<\/td>\n\/CNTA<\/td>\n<\/tr>\n
Gnd<\/td>\n6<\/td>\n14<\/td>\n\/CNTB<\/td>\n<\/tr>\n
Gnd<\/td>\n7<\/td>\n15<\/td>\n\/ROMDIS<\/td>\n<\/tr>\n
Gnd<\/td>\n8<\/td>\n16<\/td>\n\/RADR<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

 <\/p>\n

CN2 - to hard disk<\/b><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Gnd<\/td>\n1<\/td>\n2<\/td>\n\/READ<\/td>\n<\/tr>\n
Gnd<\/td>\n3<\/td>\n4<\/td>\n\/WRITE<\/td>\n<\/tr>\n
Gnd<\/td>\n5<\/td>\n6<\/td>\nReserved<\/td>\n<\/tr>\n
\/SELECT<\/td>\n7<\/td>\n8<\/td>\n\/SHIP_READY<\/td>\n<\/tr>\n
Gnd<\/td>\n9<\/td>\n10<\/td>\n\/WRITE_GATE<\/td>\n<\/tr>\n
\/MOTOR_ON<\/td>\n11<\/td>\n12<\/td>\n\/HEAD_1<\/td>\n<\/tr>\n
\/DIR_IN<\/td>\n13<\/td>\n14<\/td>\n\/STEP<\/td>\n<\/tr>\n
\/WRITE_FAULT<\/td>\n15<\/td>\n16<\/td>\n\/SEEK_COMPLETE<\/td>\n<\/tr>\n
\/SERVO_GATE<\/td>\n17<\/td>\n18<\/td>\n\/INDEX<\/td>\n<\/tr>\n
\/TRACK_0<\/td>\n19<\/td>\n20<\/td>\n\/READY<\/td>\n<\/tr>\n
Gnd<\/td>\n21<\/td>\n22<\/td>\n5V<\/td>\n<\/tr>\n
Gnd<\/td>\n23<\/td>\n24<\/td>\n5V<\/td>\n<\/tr>\n
Gnd<\/td>\n25<\/td>\n26<\/td>\n12V<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

 <\/p>\n

\n

Expansion Bus Connector<\/b><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
RESET<\/td>\n1<\/td>\n2<\/td>\nD7<\/td>\n<\/tr>\n
Gnd<\/i><\/td>\n3<\/td>\n4<\/td>\nD6<\/td>\n<\/tr>\n
IRQ2<\/td>\n5<\/td>\n6<\/td>\nD5<\/td>\n<\/tr>\n
Power On<\/i><\/td>\n7<\/td>\n8<\/td>\nD4<\/td>\n<\/tr>\n
DRQ2<\/td>\n9<\/td>\n10<\/td>\nD3<\/td>\n<\/tr>\n
Gnd<\/i><\/td>\n11<\/td>\n12<\/td>\nD2<\/td>\n<\/tr>\n
\/IO CH CHK<\/i><\/td>\n13<\/td>\n14<\/td>\nD1<\/td>\n<\/tr>\n
Gnd<\/i><\/td>\n15<\/td>\n16<\/td>\nD0<\/td>\n<\/tr>\n
Gnd<\/td>\n17<\/td>\n18<\/td>\nIO CH RDY<\/td>\n<\/tr>\n
\/SMEMW<\/td>\n19<\/td>\n20<\/td>\nAEN<\/td>\n<\/tr>\n
\/SMEMR<\/td>\n21<\/td>\n22<\/td>\nA19<\/td>\n<\/tr>\n
\/IOWR<\/td>\n23<\/td>\n24<\/td>\nA18<\/td>\n<\/tr>\n
\/IORD<\/td>\n25<\/td>\n26<\/td>\nA17<\/td>\n<\/tr>\n
\/DACK3<\/td>\n27<\/td>\n28<\/td>\nA16<\/td>\n<\/tr>\n
DRQ3<\/td>\n29<\/td>\n30<\/td>\nA15<\/td>\n<\/tr>\n
\/DACK1<\/td>\n31<\/td>\n32<\/td>\nA14<\/td>\n<\/tr>\n
DRQ1<\/td>\n33<\/td>\n34<\/td>\nA13<\/td>\n<\/tr>\n
\/REFRESH<\/td>\n35<\/td>\n36<\/td>\nA12<\/td>\n<\/tr>\n
CLOCK<\/td>\n37<\/td>\n38<\/td>\nA11<\/td>\n<\/tr>\n
IRQ7<\/td>\n39<\/td>\n40<\/td>\nA10<\/td>\n<\/tr>\n
IRQ6<\/td>\n41<\/td>\n42<\/td>\nA9<\/td>\n<\/tr>\n
IRQ5<\/td>\n43<\/td>\n44<\/td>\nA8<\/td>\n<\/tr>\n
IRQ4<\/td>\n45<\/td>\n46<\/td>\nA7<\/td>\n<\/tr>\n
IRQ3<\/td>\n47<\/td>\n48<\/td>\nA6<\/td>\n<\/tr>\n
\/DACK2<\/td>\n49<\/td>\n50<\/td>\nA5<\/td>\n<\/tr>\n
TC<\/td>\n51<\/td>\n52<\/td>\nA4<\/td>\n<\/tr>\n
ALE<\/td>\n53<\/td>\n54<\/td>\nA3<\/td>\n<\/tr>\n
Gnd<\/i><\/td>\n55<\/td>\n56<\/td>\nA2<\/td>\n<\/tr>\n
OSC<\/td>\n57<\/td>\n58<\/td>\nA1<\/td>\n<\/tr>\n
Gnd<\/td>\n59<\/td>\n60<\/td>\nA0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Italics<\/i> indicate differences in pinout to the standard ISA pinout<\/p>\n

Pin 7 appears to be a 4.7k pull-up to Vcc, presumably to indicate when the system is powered on<\/p>\n","protected":false},"excerpt":{"rendered":"

Retrochallenge RC2017\/04 might be over, but I’m going to try and keep moving on this project. I’d already started on the pinout for the internal connectors used by the hard disk controller, and finishing that off seemed like a fairly straightforward task. Having done that, the Expansion Bus header on the back of the system […]<\/p>\n","protected":false},"author":1,"featured_media":329,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ngg_post_thumbnail":0,"footnotes":""},"categories":[4],"tags":[8],"class_list":["post-328","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-retrocomputing","tag-v86p"],"_links":{"self":[{"href":"https:\/\/knm.org.uk\/blog\/wp-json\/wp\/v2\/posts\/328","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/knm.org.uk\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/knm.org.uk\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/knm.org.uk\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/knm.org.uk\/blog\/wp-json\/wp\/v2\/comments?post=328"}],"version-history":[{"count":1,"href":"https:\/\/knm.org.uk\/blog\/wp-json\/wp\/v2\/posts\/328\/revisions"}],"predecessor-version":[{"id":330,"href":"https:\/\/knm.org.uk\/blog\/wp-json\/wp\/v2\/posts\/328\/revisions\/330"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/knm.org.uk\/blog\/wp-json\/wp\/v2\/media\/329"}],"wp:attachment":[{"href":"https:\/\/knm.org.uk\/blog\/wp-json\/wp\/v2\/media?parent=328"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/knm.org.uk\/blog\/wp-json\/wp\/v2\/categories?post=328"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/knm.org.uk\/blog\/wp-json\/wp\/v2\/tags?post=328"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}